The present invention relates to a method for fabricating a semiconductor device, and in particular to a method for fabricating a capacitor of a semiconductor device which can improve stability and reduce capacitance of a bit line, by enhancing an insulation property between the bit line and a storage electrode and a margin in the formation process of a storage electrode contact.
Recently, the high integration tendency of the semiconductor device has been remarkably influenced by development of minute pattern formation techniques. It is essential to miniaturize a photoresist film pattern that has been widely used as a mask for an etching or ion implantation step in the fabrication process of the semiconductor device.
Resolution (R) of the photoresist film pattern is proportional to a wavelength (xcex) of a light source of a miniature exposer and a process variable (k), and inversely proportional to a numerical aperture (NA) of the exposer.
[R=k*xcex/NA, R=resolution, xcex=wavelength of light source, NA=numerical aperture]
Here, the wavelength of the light source is reduced to improve photodecomposition of the miniature exposer. For example, the resolution of G-line miniature exposer having a wavelength of 436 nm is about 0.7 xcexcm, and the resolution of i-line miniature exposer having a wavelength of 365 nm is about 0.5 xcexcm. In order to form a minute pattern below 0.5 xcexcm, there have been developed a method of employing an exposer using a deep ultra violet ray (DUV) having a small wavelength, such as a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, a method of using a phase shift mask as a photo mask, a contrast enhancement layer (CEL) method of forming a thin film for enhancing an image contrast on a wafer, a tri-layer resist (TLR) method of positioning an intermediate layer such as SOG between the two photoresist films, and a silylation method of selectively implanting silicon into an upper side of the photoresist film.
In addition, according to the high integration of the semiconductor device, a size of a contact hole connecting upper and lower conductive interconnections and an interval between the contact hole and the peripheral interconnections are decreased, and an aspect ratio, a rate of a diameter and a depth of the contact hole is increased.
As a result, in the high integration semiconductor device including multi-layer conductive interconnections, it is necessary to precisely strictly align the masks so as to form the contact hole, which results in reduced redundancy of the process.
Accordingly, the masks are formed in consideration of misalignment tolerance in a mask alignment step, lens distortion in an exposure step, critical dimension variation in mask formation and photoetching steps and registration among the masks.
There has been also suggested a self aligned contact (SAC) technique of forming the contact hole according to a self aligned method in order to overcome the limitation of a lithography process in the contact hole formation.
According to the SAC method, a polycrystalline silicon layer, a nitride film or an oxide nitride film may be used as an etching barrier film. Preferably, the nitride film may be employed as the etching barrier film.
A conventional method for fabricating a capacitor of a semiconductor device will now be described, which will not be illustrated in the drawings.
A predetermined substructure, for instance, a device isolation insulating film, a gate insulating film and a MOS field effect transistor (MOSFET) having a gate electrode overlapped with a mask oxide film pattern and source/drain regions are formed on the semiconductor wafer. Thereafter, an etching barrier film and an interlayer insulating film consisting of an oxide film are sequentially stacked on the whole surface of the resultant structure.
A contact hole is formed by forming a photoresist film pattern exposing the interlayer insulating film at a region of the semiconductor wafer where a contact of a storage electrode or bit line will be formed, exposing the etching barrier film by dry-etching the interlayer insulating film exposed by the photoresist film pattern, and re-etching the etching barrier film.
Here, when the polycrystalline silicon is used as the etching barrier film, the etching barrier film may be formed on the whole surface, or a polycrystalline silicon layer pad may be formed at a region where the contact hole will be formed.
The polycrystalline silicon SAC method employs as the etching barrier film the polycrystalline silicon having a different etching layer from the oxide film, thereby increasing an etching selection ratio difference between the polycrystalline silicon and the oxide film.
However, the whole surface deposition method may lower insulation reliability between the contact holes, and the pad formation method may damage the wafer when misalignment takes place between the contact pad and the silicon wafer.
A method for expanding the contact pad by using a spacer or polymer has been suggested to prevent the wafer from being damaged. However, this method is impossible to implement a design rule of xe2x80x9cbelow 0.18 xcexcmxe2x80x9d.
The SAC method of employing the nitride film as the etching barrier film has been suggested in order to overcome such a disadvantage.
In a state where the etching selection ratio of the interlayer insulating film and the etching barrier film is at least 5:1, the SAC method removes the nitride film according to the dry etching step, thereby forming the contact hole.
In order to increase the etching selection ratio, the etching step uses a Cxe2x80x94Hxe2x80x94F gas generating a large amount of polymer or a gas including hydrogen, mixedly with an inactive gas.
In general, the interlayer insulating film consists of a BPSG film having excellent mobility, and thus the cell and peripheral circuit units have superior planarization and gap-fill properties.
A bit line is defined on the BPSG film. The BPSG film that is positioned lower is exposed. Here, the bit line may be shifted or bent differently from the definition on the mask due to the stress resulting from a material difference between the bit line and the BPSG film.
In case the bit lines are formed at regular intervals, the stress between the materials is constant. However, an outermost line of the pattern or a separated bit line may be shifted or bent. Accordingly, a short phenomenon may occur on the metal interconnection contact or storage electrode contact, which results in a fatal fail in the chip.
In addition, according to the high integration of the semiconductor device, a size of the cell is decreased. Thus, a height of the storage electrode is increased to obtain sufficient capacitance. As a result, the aspect ratio rises, and the excess etching step is required.
There is a high possibility of generating the short phenomenon between the devices. As a size of the device becomes smaller, it is difficult to obtain a process margin and an open area of the contact when forming the contact. As the open area of the contact becomes smaller, a contact resistance is increased, and thus an operational speed of the device is decreased.
Accordingly, it is a primary object of the present invention to provide a method for fabricating a capacitor of a semiconductor device which can prevent a shift phenomenon of a bit line from occurring, by forming a strong pad insulating film having low mobility on a BPSG film in order to reduce the stress between the bit line and the BPSG film that is a lower interlayer insulating film.
In addition, it is another object of the present invention to provide a method for fabricating a capacitor of a semiconductor device which can prevent a short phenomenon from being generated between a storage electrode and a bit line and which can prevent capacitance of the bit line from being increasing, by forming a storage electrode contact plug and the storage electrode according to a self-aligned contact (SAC) method after the formation of the bit line.
In order to achieve the above-described objects of the present invention, a method for forming a capacitor of a semiconductor device comprises the steps of: forming a first interlayer insulating film having a contact plug connecting to a region of a semiconductor wafer where a predetermined substructure is formed, a bit line contact and a storage electrode contact being formed in the region; forming a pad insulating film on the whole surface of the resultant structure having the contact plug and the first interlayer insulating film; forming a stacked structure of a polycrystalline silicon layer, a silicide film and a mask insulating film on the pad insulating film; forming a bit line by etching the stacked structure having the pad insulating film by using a bit line mask as an etching mask; forming an insulating film spacer at the sidewall of the bit line; forming a second interlayer insulating film having a storage electrode contact hole on the bit line; forming the storage electrode contact to be filled in the storage electrode contact hole; and for forming a storage electrode connecting to the storage electrode contact.
In addition, in order to achieve the above-described objects of the present invention, a method for forming a capacitor of a semiconductor device comprises: forming a first interlayer insulating film having a contact plug connecting to a region of a semiconductor wafer where a predetermined substructure is formed, a bit line contact and a storage electrode contact being formed in the region; forming a pad insulating film on the whole surface of the resultant structure having the contact plug and the first interlayer insulating film; forming a stacked structure of a polycrystalline silicon layer, a silicide layer and a mask insulating film on the pad insulating film, and forming a bit line by etching the stacked structure having the pad insulating film by using a bit line mask as an etching mask; forming a first insulating film spacer at the sidewall of the bit line; forming a second interlayer insulating film on the whole surface of the resultant structure; keeping the second interlayer insulating film having a predetermined thickness between the first insulating film spacers, by full-etching the second interlayer insulating film; forming a second insulating film spacer at the sidewall of the residual first insulating film spacer; forming a third interlayer insulating film having an etching selection ratio difference from the second interlayer insulating film on the whole surface of the resultant structure; exposing an upper portion of the second interlayer insulating film by selectively etching the third interlayer insulating film by using a storage electrode contact mask as an etching mask; forming a storage electrode contact hole exposing the contact plug by removing the second interlayer insulating film; forming the storage electrode contact to be filled in the storage electrode contact hole; and forming a storage electrode connecting to the storage electrode contact.